That camp is occupied almost entirely by Donald Thomas’ book, Logic Design and Verification Using SystemVerilog (Revised) .
Bridging the gap between RTL design and rigorous verification for the working engineer and the advanced student. If you are a digital design engineer, a verification engineer moving closer to the design side, or a graduate student trying to survive the complexities of modern ASIC/FPGA flow, you know the struggle. That camp is occupied almost entirely by Donald
You need to design a pipeline. You write the RTL, but you spend 80% of your time writing the testbench. This book helps you flip that ratio. You need to design a pipeline
Absolute beginners who have never written an if statement in hardware. You need a basic Verilog primer first (like Ashenden’s Digital Design ). A Minor Critique (Nothing is perfect) The book assumes a level of academic patience. Thomas writes like a professor (he is one, at Carnegie Mellon legacy). The examples are lean—sometimes too lean. He avoids the "kitchen sink" examples that bloated other textbooks, but occasionally you wish he had drawn the waveform diagram for a particularly tricky race condition. Absolute beginners who have never written an if
Beyond the Schematic: Why Donald Thomas’ “Logic Design and Verification Using SystemVerilog” is a Modern Classic
9.5/10 (Deducted half a point because the index could be more thorough).